The goal of this lecture is to introduce all major synthesis-steps from the register-transfer level down to the physical level and the key algorithms at each step respectively, such as:

• Logic Minimization
• Mapping (e.g. FlowMap)
• Placement (e.g. Simulated Annealing, Genetic Algorithms)
• Routing (e.g. PathFinder)

• Basic knowledge of hardware-synthesis - based on an hardware description language. (E.g.: Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl or Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design).
• Basic knowledge of an object-oriented programming language, preferably Java.

The slides used in the lecure are provided in the Moodle course.