The goal of this lecture is to introduce all major synthesis-steps from the register-transfer level down to the physical level and the key algorithms at each step respectively, such as:

• Logic Minimization
• Mapping (e.g. FlowMap)
• Placement (e.g. Simulated Annealing, Genetic Algorithms)
• Routing (e.g. PathFinder)

Attention:

Due to a sabbatical in summer semester 2019, Prof. Hochberger will not hold the weekly lectures. Instead, we offer the recordings from last year and the slides for self study. The exercises will be supervised by Dennis Wolf in the usual way.

In the first week of the semester there will be an administrative meeting (17th April, 11:40 a.m. in S306/053) to answer all upcoming questions. In summer semester 2020 the lecture will again be offered in the usual form.

• Basic knowledge of hardware-synthesis - based on an hardware description language. (E.g.: Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl or Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design).
• Basic knowledge of an object-oriented programming language, preferably Java.

The slides used as lecture materials can be downloaded from moodle.

Examination dates and procedures