Open theses and research assistant jobs

Bachelor theses

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Architektur-agnostisches Loop-Profiling mit Qemu User-Space Emulator
C/C++ Software Praktisch
Ansprechpartner: Ramon Wirsch,  Frühester Beginn: sofort
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IBM Z-Architektur User-Space Simulator
Java Software Praktisch
Ansprechpartner: Ramon Wirsch,  Frühester Beginn: sofort
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RISC-V User-Space Simulator
Java Software Praktisch
Ansprechpartner: Ramon Wirsch,  Frühester Beginn: sofort
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Analyse und Optimierung des SpartanMC Befehlssatzes
C/C++ Verilog Software Praktisch Theoretisch
Ansprechpartner: Jakob Wenzel,  Frühester Beginn: sofort
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Portierung der SpartanMC Benchmark Suite auf Vivado HLS
C/C++ Hardware Software Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Master theses

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Runtime Decoupling von Memory Dependencies
C/C++ Software Praktisch Englisch Deutsch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Project seminars bachelor

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Entkoppeln von Nicht Strikten Speicherzugriffen
C/C++ Software Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort
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Portierung der CHStone Benchmark Suite auf SpartanMC
C/C++ Software Praktisch
Ansprechpartner: Johanna Rohde,  Frühester Beginn: sofort

Project seminars master

  • Unfortunately there is nothing available in this category at the moment

Research assistant jobs

  • Unfortunately there is nothing available in this category at the moment

Information on Project Seminars

The Project Seminars listed here are only assigned to students who do not major in Computer Engineering (B.Sc. ETiT). Students who major in Computer Engineering have to do the Project Seminar in combination with the Bachelor Thesis and have therefore to be handled differently.

Contact

Technische Universität Darmstadt

Department of Electrical Engineering and Information Technology

Computer Systems Group

Prof. Dr.-Ing. Christian Hochberger

Merckstr. 25

64283 Darmstadt

+49 6151 16-21150

+49 6151 16-21150

Key

Good knowledge in C required
Good knowledge in Java required
Good knowledge in Verilog required
Good knowledge in VHDL required
Hardware oriented thesis
Software oriented thesis
Practical thesis
Theoretical thesis
Report should be written in English
Report should be written in German
Additional HW/SW required
Demanding thesis
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