Lecture "High-Level Synthesis"

Content

  • Mapping of behavioral descriptions (e.g. in the form of program fragments) on FPGA and CGRA structures
  • Sub-tasks allocation, scheduling, binding
  • Exact or heuristic solutions
  • Design principles of heuristic solutions

Organisation

Typ: Lecture (V2)
Date: Wed, 9:50-11:30
Room: S3 06 / 053
Begin: 18.10.2017
Lecturer: Prof. Dr.-Ing. Christian Hochberger
CP: see TUCaN
Cycle: every winter semester
Language: english

Prerequisites

  • Knowledge of hardware synthesis on the basis of at least one hardware description lan-guage is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog HDL oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design).
  • The student should have basic knowledge of at least one object oriented programming lan-guage, preferably Java

Exercise

Date: Mon, 16:15-17:55
Begin: 23.10.2017
Room: S3 06 / 053
Lecturer: Prof. Dr.-Ing. Christian Hochberger

Exam

Exam Information:

Contact

Technische Universität Darmstadt

Department of Electrical Engineering and Information Technology

Computer Systems Group

Prof. Dr.-Ing. Christian Hochberger

Merckstr. 25

64283 Darmstadt

+49 6151 16-21150

+49 6151 16-21150

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