Die Veranstaltung findet bis auf weiteres nicht statt.

1. Processor execution. Sources of performance loss, latency. Possible techniques to im-prove performance. Simultaneous multi-threading as an established solution. Motivation for multi-threading – p-threads as a model of execution in SW, micro-threading as a model of execution in HW.
2. Definition of micro-threading, its requirements on the microarchitecture. Microthreaded assembly instructions, design alternatives for extended instruction sets. Required support in micro-architecture – self-synchronizing register file, cache controllers, thread scheduler.
3. Execution in the micro-threaded pipeline. Interaction between cache controllers, register file, thread scheduler, integer pipeline. Data dependences between threads and its influence on execution (embarrassingly parallel vs. sequential programs). Interaction with legacy code, execution modes, OS support.
4. Developing for the real world: Writing testbenches. Performance profiling. Indicators of efficient silicon use.
5. Microthreading in multi-core architectures. Big issues: Scalability, sufficient parallelism, trade-off between clock frequency and access latency.

A script is available as a published book and English slides can be obtained through moodle.

Hands-on experience with at least one of Verilog or VHDL is expected. Basic understanding of FPGA technology and thorough knowledge of digital circuit design and computer architecture. Several tools used throughout the labs might require additional programming languages and tools (Perl, C, bash). This knowledge can be obtained during the labs.