Boris Dreyer

M.Sc. Boris Dreyer

Merckstraße 25
64283 Darmstadt

Vorträge

2016

Hardware Support for Histogram-based Performance Analysis, Resource Aware Computing 2016, Eindhoven, Netherlands

Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs, Worst-Case Execution Time Analysis 2016, Toulouse, France

2015

Combining Runtime Verification and Execution Time Estimation, Solutions for MultiCore Debug Conference 2015, Munich, Germany

Veröffentlichungen