A Superscalar Version of the DLX Processor
Superscalar DLX Features
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Superscalar DLX Features
- Pipelined, superscalar
-
Two instructions per clock
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Branch-Target buffer
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Reorder-Buffer to commit instructions in program order
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Precise exception processing
- Four execution units with Reservation-Station
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Branch-Resolve unit
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Arithmetic-Logic unit
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Multiply-Divide unit
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Load-Store unit
- Write-Buffer
- 64 byte Instruction-Cache
- 64 byte Data-Cache
- 4 entry Instruction-Address-Translation-Buffer, page
size: 128 byte
- 4 entry Data-Address-Translation-Buffer, page size:
128 byte
Note:
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The small caches and address translation buffers increase
simulation performance and can be filled up quickly by little test programs.
Download
You can download PostScript
or PDF files of the german documentation. The
instruction flow through the pipeline, the design steps and the design
unit interfaces are illustrated in many figures.
Compiling the VHDL description
enables you to simulate test programs.
An assembler for the DLX processor an other support material
is available at http://www.ashenden.com.au/designers-guide/DG-DLX-material.html.
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