A Superscalar Version of the DLX Processor

Superscalar DLX Features

DLX Block Diagram

Superscalar DLX Features

- Pipelined, superscalar - Four execution units with Reservation-Station - Write-Buffer
- 64 byte Instruction-Cache
- 64 byte Data-Cache
- 4 entry Instruction-Address-Translation-Buffer, page size: 128 byte
- 4 entry Data-Address-Translation-Buffer, page size: 128 byte



You can download PostScript or PDF files of the german documentation. The instruction flow through the pipeline, the design steps and the design unit interfaces are illustrated in many figures.
Compiling the VHDL description enables you to simulate test programs.
An assembler for the DLX processor an other support material is available at http://www.ashenden.com.au/designers-guide/DG-DLX-material.html.