W. Günther, R. Drechsler and S. Höreth, "Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation", in International Conference on Computer Design (ICCD2000), Austin, Texas, Sept. 2000.
1999
S. Höreth and R. Drechsler, "Formal Verification of Word-Level Specifications", in Design Automation and TEst Conference (DATE '99), Munich, March 1999.
1998
S.Hoereth, C.Blank: "TUD Decision Diagram Package, Preliminary C Programmers Manual", Manual, Darmstadt University of Technology, Dept. of Electrical and Computer Engineering, Computer Systems, Germany, 1998. Online Document
S. Höreth and R. Drechsler, "Dynamic Minimization of Word-Level Decision Diagrams", in Design Automation and TEst Conference (DATE '98), Paris, February 1998.
R. Drechsler and S. Höreth , "Manipulation of *BMDs", in Asian and South-Pacific Design Automation Conference (ASP-DAC'98), Yokohama, Japan, February 1998.
1997
S. Höreth, "Implementation of a Multiple-Domain Decision Diagram Package", in Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME '97) (E. Cerny and D.K. Probst, editors), pp. 185-202, Montreal, Canada, October 1997. IFIP WG 10.5, Chapman and Hall.
S. Höreth and R. Drechsler, "Fast Construction of Kronecker Decision Diagrams from Library Based Circuits", in The Seventh Workshop on Synthesis and System Integration of MIxed Technologies (SASIMI '97), Osaka, Japan, December 1997.
S. Höreth and R. Drechsler, "Compilation of Fast Manipulation Algorithms for K*BMDs", in 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (Reed-Muller '97), Oxford, September 1997, FZI report 5/97 Karlsruhe/Germany.
S. Höreth , "Graphbasierte Verifikation kombinatorischer Schaltnetze unter Verwendung von Bausteinbibliotheken", in 5. GI/ITG/GMM Workshop Methoden des Entwurfs und der Verifikation digitaler Systeme (R. Hagelauer, editor) , Linz, Österreich, April 1997, Universitätsverlag Trauner.
1996
S. Höreth, "Compilation of Optimized OBDD Manipulation Algorithms ", in European Design Automation Conference (EuroDAC '96), pp. 152-157, Geneva, Switzerland, September 1996.
S. Höreth , "A Compilation Method for the Synthesis of Decision Diagrams from Combinational Circuits", THD-RS-96-1, TU Darmstadt. (PostScript)
1995
S. Höreth , "N-äre Dekompositionen und kanonische Funktionsgraphen", in 3. GI/ITG Workshop zur Anwendung formaler Methoden beim Entwurf von Hardwaresystemen (W. Grass and M. Mutz, editors) , Berichte aus der Informatik, pp. 71-78, Passau, March 1995. GI/ITG, Shaker Verlag.
1994
S. Höreth , "MBDDs - Hierarchische Entscheidungsgraphen zur Darstellung und Manipulation Boolescher Funktionen", in GI/ITG Workshop Anwendung Formaler Methoden im Systementwurf. GI/ITG, Universität Frankfurt, Interner Bericht Nr. 6/94, March 1994.
1993
H. Eveking and S. Höreth, "Optimization and Resynthesis of Complex Data-Paths", in 30th Design Automation Conference, pp. 637-641, Dallas, Texas, 1993.
1992
H. Eveking and S. Höreth , "Optimierung und Resynthese komplexer Datenpfade", in ITG Fachbericht 122, Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, S. 115-124, 1992.
